삼성전자 자회사이자 ‘지노브 존(Zinnov Zones) 2018’에서 최고의 IoT 서비스 리더로 선정된 Harman Connected Services (하만) 한국 지사에서 SOC/ASIC - Physical Design Engineer 분을 (경력 4년~15년) 모시고 있습니다. 영어는 독해가 가능하시면 지원 가능합니다.
- Floorplan, P&R, ECO, Physical verification (DRC/LVS/DFM etc), IR_DROP check
- PD(Backend) tools: ICC2(Major) or Innovus, STAR_RCXT, Calibre, Redhawk
[지원방법] ResumeHCSKR@harman.com 메일로 영문 이력서 송부
- Above Bachelor's Degree
- 4 years and above related work experience
- Experience in block level/full chip Physical Design activities.
- Basic Knowledge on VLSI and basic Knowledge on Timing.
- Hands on Experience in areas of physical verification (DRC/LVS/ERC/ANT) using Calibre or equivalent.
- Proficiency in Tcl and Perl scripting is essential.
- Hands on Experience in ICC, Innovus or equivalent.
- Experience on PrimeTime, StarRC-XT, Formality, Redhawk or equivalent will be preferred.
- Self-motivated team player with strong problem-solving skills that can collaborate with various teams to achieve design goals.
- Responsible for floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing analysis, Power and Signal Integrity Analysis and
- Physical Verification of Low power and high frequency designs.
- Extensive experience and detailed knowledge in Cadence or Synopsys or Physical Design Tools
- Desired skills- Provide technical guidance, Leadership quality
- Should have been familiarity with process node
Guidelines for Applicants
- 전형방법 :
- 1차 서류전형
- 제출서류 :
- 영문이력서 (각종 증빙서류는 서류전형합격자에 한해 추후제출)